The saturation current with no applied gate voltage, I.sub.dss, between the source and drain of a field effect transistor (FET) is an important parameter of an FET. The value of I.sub.dss for a particular FET is process dependent. The value of source drain current when a gate voltage is applied, I.sub.ds is dependent on the characteristic I.sub.dss of the device; as I.sub.dss increases so does I.sub.dss.
Various techniques, such as carefully controlling process variables or using large source resistors for biasing, have been proposed to limit the variation or effect of variation of I.sub.dss. However, controlling I.sub.dss in process lowers yield and using large resistors increases power dissipation.
Accordingly, techniques to increase the I.sub.dss window are needed to increase yield.